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IBM-AUSTRIA - PC-HW-Support 30 Aug 1999 |
The IEEE 1284-1994 Standard (Parallel Port)
Introduction to the IEE 1284-1994 Standard
Parallel Port Background
When IBM introduced the PC, in 1981, the parallel printer port was
included as an alternative to the slower serial port as a means for
driving the latest high performance dot matrix printers. The parallel
port had the capability to transfer 8 bits of data at time whereas the
serial port transmitted one bit at a time. When the PC was introduced,
dot matrix printers were the main peripheral that used the parallel
port. As technology progressed and the need for greater external
connectivity increased, the parallel port became the means by which you
could connect higher performance peripherals. These peripherals now
range from printer sharing devices, portable disk drives and tape
backup to local area network adapters and CD ROM players.
The problems faced by developers and customers of these peripherals
fall into three categories. First, although the performance of the PC
has increased dramatically, there has been virtually no change in the
parallel port performance or architecture. The maximum data transfer
rate achievable with this architecture is around 150 kilobytes per
second and is extremely software intensive. Second, there is no
standard for the electrical interface. This causes many problems when
attempting to guarantee operation across various platforms. Finally,
the lack of design standards forced a distance limitation of only 6 feet
for external cables.
In 1991 there was a meeting of printer manufactures to start
discussions on developing a new standard for the intelligent control of
printers over a network. These manufactures, which included Lexmark,
IBM, Texas Instruments and others, formed the Network Printing Alliance.
The NPA defined a set of parameters that, when implemented in the
printer and host, will allow for the complete control of printer
applications and jobs.
While this work was in progress it became apparent that to fully
implement this standard would require a high performance bi-directional
connection to the PC. The usual means of connection, the ordinary PC
parallel port, did not have the capabilities required to meet the full
requirements or abilities of this standard.
The NPA submitted a proposal to the IEEE for the creation of a
committee to develop a new standard for a high speed bi-directional
parallel port for the PC. It was a requirement that this new standard
would remain fully compatible with the original parallel port software
and peripherals, but would increase the data rate capability to greater
than 1M bytes per second, both in and out of the computer. This
committee became the IEEE 1284 committee.
The IEEE 1284 standard, 'Standard Signaling Method for a
Bi-directional Parallel Peripheral Interface for Personal Computers' ,
was approved for final release in March of 1994.
The Parallel Port -- an Overview
The parallel port, as implemented on the PC, consists of a connector
with 17 signal lines and 8 ground lines. The signal lines are divided
into three groups:
- Control (4 lines)
- Status (5 lines)
- Data (8 lines)
As originally designed, the Control lines are used as interface control
and handshaking signals from the PC to the printer. The Status lines
are used for handshake signals and as status indicators for such things
as paper empty, busy indication and interface or peripheral errors.
The data lines are used to provide data from the PC to the printer, in
that direction only. Later implementations of the parallel port
allowed for data to be driven from the peripheral to the PC.
Table 1 identifies each of these signals and gives their Standard
Parallel Port (SPP) definitions. The signals within these groups are
assigned to specific bits within the registers that make up the
hardware/software interface to the parallel port. The parallel port is
mapped into the I/O space of the PC. The registers consist as a
contiguous block of 3 registers starting from the parallel port's base
address. These ports are commonly referred to as the LPT ports and have
the familiar I/O base addresses of 3BCh, 378h and 278h. Newer
implementations of the parallel port, that support the advanced modes of
the 1284 standard, use 8 to 16 registers and are located at I/O
addresses 378h or 278h, or are re-locatable, as in the case of a Plug
and Play compliant parallel adapter.
Table 2 identifies the registers for the standard parallel port.
The basic method of transferring data to the printer using this port is
described in the section entitled 'Compatibility Mode.'
Table 1 -- SPP Signal Definitions (Note 1)
| Group |
SPP Signal |
In/Out |
Signal Description |
| Control |
nSTROBE |
Out |
Active low. Indicates valid data is on the data lines. |
| - |
nAUTOFEED |
Out |
Active low. Instructs the printer to automatically
insert a line feed for each carriage return |
| - |
nSELECTIN |
Out |
Active low. Used to indicate to the printer that it
is selected. |
| - |
nINIT |
Out |
Active low. Used to reset the printer. |
| Status |
nACK |
In |
A low asserted pulse used to indicate that the last
character was received. |
| |
BUSY |
In |
A high signal asserted by the printer to indicate that
it is busy and cannot take data. |
| - |
PE |
In |
Paper Empty |
| - |
SELECT |
In |
Asserted high to indicate that the printer is online. |
| - |
nERROR |
In |
Asserted low to indicate that some error condition
exists |
| Data |
DATA[8:1] |
Out |
8 data lines- output only in older SPP |
(Note 1) The signal usage described in this and all following
tables define the usage while in the described data transfer mode.
Many of these signals are used for mode transitions and for additional
status information. Please refer to the IEEE 1284-1994 standard for the
complete definition and usage of these signals. This is meant as an
introduction only.
Table 2 -- SPP Register Definition
Register
Offset (2) |
Name |
Read/Write |
Description |
| 0 |
Data
Register |
R/W |
Data port to read or write data |
| 1 |
Status
Register |
R |
Contains status bits |
| 2 |
Control
Register |
W |
Used to set control signals |
| 3-7 |
Various |
N/A |
Used differently by various implementations |
(Note 2) This is the offset from the base address of the port.
IEEE 1284 Data Transfer Modes
The use of the various 1284 data transfer modes provide the capability
to create a forward and reverse channel connection between the host
computer and an attached peripheral. Since there is only one set of
data lines the connection is half duplex, data is transferred in one
direction at a time.
The Compatiblity and Nibble modes of operation can be implemented in
any existing parallel port in order to create a complete bi-directional
communication path between the host and peripheral. The Compatibility
and Byte modes can also be used create a bi-directional communication
path, but the the parallel port must support the Byte mode capability.
The Byte mode requires that an entire byte of data can be read from the
external data lines. This is usually implemented by the addition of a
direction bit in the parallel port's Control register. This type of
port is generally called a 'bi-directional' parallel port.
The EPP and ECP modes have bi-directional capability as part of
their protocol. These modes require that the hardware implement a
state machine that is capable of automatically generating the control
strobes that are necessary for these high performance data transfer
modes.
Each of the operating modes, other than Compatibility, rename the
control and status signals to have meaning within the mode being used.
The discussions for each mode will use the names consistant with the
mode being discussed.
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