Return to MAIN-Index  Return to SUB-Index    IBM-AUSTRIA - PC-HW-Support    30 Aug 1999

Checkpoint Codes




Checkpoint Codes

During POST, the computer displays the status of the components being tested in the form of Checkpoint (CP) codes in the lower left-hand corner of the screen. The following is a list of the CP codes followed by the routine in process and the boot mode.

CP Code Routine Boot Mode
01 Its_A_Reset Cold+Warm+Restore+Mfg+SAD
0D Init Chip_NS Cold+Warm+Restore+Mfg+SAD
12 Periph Init Cold+Warm+Restore+Mfg+SAD
03 Disable Video Cold+Warm+Restore+Mfg+SAD
05 Phase 1 Enter Big Real Cold+Warm+Restore+Mfg+SAD
B0 Enable Local APIC Cold+Warm+Restore+Mfg+SAD
06 Cache Init Cold+Warm+Restore+Mfg+SAD
07 Init Refresh Cold+Restore+Mfg
08 Wait For RTC Cold+Restore+Mfg
0A Std CMOS Checksum NS Cold+Warm+Restore+Mfg
0B Mid CMOS Checksum NS Cold+Warm+Restore+Mfg
0C Ext CMOS Checksum NS Cold+Warm+Restore+Mfg
0E C SET_INIT Cold+Warm+Restore+Mfg+SAD
10 Check Parity NonParity Cold+Warm+Restore+Mfg
11 Disable Parity Cold+Warm+Restore+Mfg+SAD
B1 Init Seattle Cold+Restore+Mfg+SAD
13 Test CPU Regs Cold+Restore+Mfg
14 Init RTC Cold+Warm+Restore+Mfg+SAD
16 Init Timer 0 Cold+Warm+Restore+Mfg+SAD
17 Init Timer 2 Cold+Warm+Restore+Mfg+SAD
18 Test DMA Cold+Warm+Restore+Mfg+SAD
19 Test Page Regs Cold+Warm+Restore+Mfg+SAD
1A Verify Refresh Cold+Restore+Mfg
1B Enable Parity Cold+Warm+Restore+Mfg+SAD
1C Save ID Warm SAD
1D Test First 64k Cold+Restore+Mfg
1E Clear First 64k Cold+Warm+Restore+Mfg
1F POST with Stack Cold+Warm+Restore+Mfg+SAD
20 Enable BIOSE000 SAD
21 BIOS Shadow Cold+Warm+Restore+Mfg
B2 Shadow SCSI Cold+Warm+Restore+Mfg
23 Phase 2 POST Cold+Warm+Restore+Mfg+SAD
24 Enable BIOS F000 SAD
24 Shadow VPD Cold+Warm+Restore+Mfg
25 Init Key Board Data Cold+Warm+Restore+Mfg+SAD
26 Save ID Cold+Warm+Restore+Mfg+SAD
B3 Check P54C Cold+Mfg
27 Init Q Boot Cold+Warm+Restore+Mfg
28 Periph Config Cold+Warm+Restore+Mfg+SAD
2A Init Timeout Tables Cold+Warm+Restore+Mfg+SAD
2B Pos_Setup Cold+Warm+Restore+Mfg
2F Test DMA Locations Cold+Warm+Restore+Mfg+SAD
B4 Init DMA Regs Cold+Warm+Restore+Mfg+SAD
30 Test PICs Cold+Warm+Restore+Mfg+SAD
31 Init Vector Table Cold+Warm+Restore+Mfg+SAD
32 Enable Timer Int Cold+Warm+Restore+Mfg+SAD
33 Init Keyboard Cold+Warm+Restore+Mfg+SAD
34 Clear Memory Size Error Cold+Restore+Mfg
35 Check Configuration Cold+Warm+Restore+Mfg
36 Mfg Boot Fork Cold+Restore+Mfg
37 PCI Reset Cold+Warm+Restore+Mfg
B5 NVRAM check Cold+Warm+Restore+Mfg
38 PCI Video Cold+Warm+Restore+Mfg
3B Sign On Cold+Warm+Restore+Mfg
3C Test Timer Tick Cold+Restore+Mfg
3F Enable Video SAD
40 CSET BFR SIZMEM Cold+Warm+Restore+Mfg+SAD
41 Size Memory Above 64k Cold+Warm+Restore+Mfg
42 CSET AFT SIZ MEM Cold+Warm+Restore+Mfg
43 Test Timer 2 Cold+Warm+Restore+Mfg
44 Password Not Entered Cold+Restore
45 Test PS/2 Mouse Cold+Warm+Restore+Mfg
46 Check For Mouse Buttons Cold+Restore
47 Init Key Board Flags Cold+Warm+Restore+Mfg+SAD
48 Test Key Board Cold+Warm+Restore
4B Memory Test Prompt Cold+Warm+Mfg
4C Test Memory Cold+Restore+Mfg
4D Clear EBDA Warm
4E CSET AFT M TEST Cold+Warm+Restore+Mfg
4F Allocate EBDA Cold+Warm+Restore+Mfg
B6 Set Planar Info Cold+Restore+
50 xfer ebda vars Cold+Warm+Restore+Mfg
B7 Init P54M Cold+Warm+Restore+Mfg
B8 Init MP Structures Cold+Warm+Restore+Mfg
B9 CPU Speed Cold+Warm+Restore+Mfg+SAD
51 Set Warm Boot Flag Warm
52 Clear Speed Bits Cold+Warm+Mfg+SAD
53 E FLOB Cold+Warm+Restore+Mfg+SAD
54 Enable System Interrupts Cold+Warm+Restore+Mfg+SAD
55 C2 Security Check Restore
56 Init Key Board Cold+Warm+Restore+SAD
57 Test RTC Cold+Warm+Restore+SAD
58 Check For NPX Cold+Warm+Restore+Mfg+SAD
59 reset hdctl Cold+Warm+Restore+Mfg+SAD
5A FD INIT Cold+Warm+Restore+Mfg+SAD
5B Set Floppy Config Cold+Warm+Restore+Mfg+SAD
BA Unlock Early Cold+Restore
5C Init A20 Cold+Warm+Restore+Mfg+SAD
5D Cache Config Cold+Warm+Restore+Mfg+SAD
5E HD SETUP Cold+Warm+Restore+Mfg+SAD
62 Verify CMOS Config Cold+Warm+Restore+Mfg
70 Check For Setup Hot Key Cold+Warm
63 Clear Screen Cold+Warm+Restore+SAD
BB Init IRQ Levels Cold+Restore
65 IBM Cirrus DDC Cold
BC PACP Arbitration Cold+Warm+Restore+Mfg+SAD
BD Enable Planar SCSI Cold+Warm+Restore+Mfg+SAD
66 CSET BFR OPROM Cold+Warm+Restore+Mfg
BE Do ROM Scan Cold+Warm+Restore
2C TCPC Cold+Warm+Restore+Mfg
49 TCPC Errors Cold+Warm+Restore
2D Find Serial Ports Cold+Warm+Restore+Mfg
2E Find Parallel Ports Cold+Warm+Restore+Mfg
68 CSET AFT OPROM Cold+Warm+Restore+Mfg
BF Get MC Data Cold+Warm+Restore
69 PCI Configure Cold+Warm+Restore+Mfg
6A MFG Hook 65 MFG
6B Init Time Of Day Cold+Warm+Restore+Mfg+SAD
6C Check For Locked Key Board Cold+Warm+Restore+SAD
6D Init Enable NMI Cold+Warm+Restore+Mfg+SAD
6E Set Boot Speed Cold+Warm+Restore+Mfg
6F Set Key Board LEDs Cold+Warm+SAD
71 Init Flush Key Board Cold+Warm+Restore+SAD
72 Move Error Log To EBDA Cold+Warm+Restore+Mfg
73 Init Disable Mouse Cold+Warm+Restore+Mfg+SAD
74 Sys Reset MFG
75 Phase 2 Exit Big Real Cold+Warm+Restore+Mfg+SAD
76 BOOT STRAP 1 Cold+Warm+MFG+SAD
78 SAD BOOT PROC SAD
79 Start Boot Sequence N/A
7A Read Boot Sector N/A
7B Boot Sector Read Complete N/A
7C Check for CE Boot Override N/A
7F Xfer to boot code N/A


The following codes also produce a series of beeps. The series of beeps are listed for each code followed by an explanation of the code.

CP Code Beeps Definition
82 1-1-3 CMOS write/read failure
83 1-1-4 BIOS ROM checksum failure
84 1-2-1 Programmable Interval Timer test failure
85 1-2-2 DMA initialization failure
86 1-2-3 DMA page register write/read test failure
87 1-2-4 RAM refresh verification failure
88 1-3-1 1st 64K RAM test failure
89 1-3-2 1st 64K RAM parity test failure
90 2-1-1 Slave DMA register test in-progress or failure
91 2-1-2 Master DMA register test in-progress or failure
92 2-1-3 Master interrupt mask register test failure
93 2-1-4 Slave interrupt mask register test failure
95 2-2-2 Key-board controller test failure
99 2-3-2 Screen memory test in-progress or failure
9A 2-3-3 Screen retrace tests in-progress or failure
9B N/A Search for video ROM in-progress
9C N/A Screen believed operable - mode in low two bits
9D N/A Screen believed operable - mode in low two bits
9E N/A Screen believed operable - mode in low two bits
9F N/A Screen believed operable - mode in low two bits
A0 3-1-1 Timer tick interrupt test failure
A1 3-1-2 Interval timer channel 2 test failure
A3 3-1-4 Time-Of-Day clock test failure
A7 3-2-4 Comparing CMOS memory size against actual
A8 3-3-1 Memory size mismatch occurred
D0 N/A Cache State
D1 N/A Cache Init
D2 N/A Cache Restore
D3 N/A Cache Config
D4 N/A Cache Flush
D5 N/A Cache Enable
D6 N/A Cache Disable
D7 N/A Cache Custom
e1h N/A CSET BFR VIDROM
e5h N/A CSET AFT CMCFG


More INFORMATION / HELP is available at the  IBM-HelpCenter

Please see the LEGAL  -  Trademark notice.
Feel free - send a Email-NOTE  for any BUG on this page found - Thank you.